- 作 者：周电著
- 出 版 社：北京：科学出版社
- 出版年份：2011
- ISBN：9787030317667
- 标注页数：394 页
- PDF页数：404 页
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Chapter 1 Introduction 1
1.1 History of Integrated Circuits 2
1.2 Roadmap of IC Technology 6
1.3 ASIC 9
1.4 Design Flow 11
1.5 CAD Tools 13
1.6 An ASIC Design Project MSDAP 17
1.7 How to Use This Book 18
1.8 Summery 19
1.9 Problems 19
References 20
Chapter 2 VLSI Design Perspective and Flow 22
2.1 Introduction 23
2.2 VLSI Technology Trend 23
2.3 SoC 26
2.4 Methodology for Custom and Semi-custom IC Design 28
2.4.1 Gate array 28
2.4.2 Standard cell 30
2.4.3 FPGA 32
2.5 Design Domain and Perspective 34
2.6 Design Flow 37
2.7 Design Task 41
2.8 Summary 43
2.9 Problems 43
References 44
Chapter 3 Specification Development 46
3.1 Introduction 47
3.2 An ASIC Project MSDAP 48
3.3 An Overall View ofthe Specific Requirement 50
3.3.1 The required computation method by the MSDAP 50
3.3.2 Additional information for the specification 53
3.4 The System Setting 54
3.5 I/O Interface and Pins 58
3.5.1 Pins and their assignments 58
3.5.2 Signal format and waveform 59
3.6 Other Issues of the Specification 62
3.7 Summary 62
3.8 Problems 62
References 64
Chapter 4 Architecture Design 65
4.1 Introduction 66
4.2 Datapath Structure 67
4.2.1 Single processor sequential structure 68
4.2.2 Multi-processor parallel structure 71
4.3 Functional Blocks and IPs 73
4.3.l IP core 74
4.3.2 Functional blocks in the MSDAP architecture 75
4.4 Time Budget and Scheduling 79
4.5 A Sample Architecture of the MSDAP Project 80
4.5.1 An architecture sample 80
4.5.2 Time budget justification of the proposed architecture 96
4.6 Summary 98
4.7 Problems 98
References 99
Chapter 5 Logic and Circuit Design 101
5.1 Introduction 102
5.2 Combinational Logics 103
5.2.1 Decoder 103
5.2.2 Encoder 106
5.2.3 Multiplexer 108
5.2.4 Arithmetic logic blocks 109
5.3 Sequential Logics 123
5.3.1 Latch and flip-flop 124
5.3.2 Shift register 136
5.3.3 Counter 138
5.3.4 FSM 144
5.4 Datapath 153
5.5 Asynchronous Circuit 156
5.6 Summery 156
5.7 Problems 156
References 158
Chapter 6 Physical Design 159
6.1 Introduction 160
6.2 Design Rules 161
6.3 Floorplan 166
6.4 Routing 171
6.4.1 Global routing 176
6.4 2 Local routing 179
6.5 Physical Layout Verification 181
6.5.1 DRC 181
6.5.2 XOR check 182
6.5.3 Antenna check 182
6.5.4 ERC 183
6.5.5 LVS check 183
6.6 Clock Network 184
6.7 Power Network 187
6.8 Engineering Change Order 189
6.9 Package 191
6.10 Summary 193
6.11 Problems 194
References 195
Chapter 7 Timing,Power,and Performance Analysis 198
7.1 Introduction 199
7.2 Buffer Insertion Mechanism 200
7.3 Transistor and Gate Sizing 203
7.3.1 Transistor sizing 203
7.3.2 Buffer sizing 203
7.3.3 Gate sizing 205
7.4 Timing Analysis 206
7.4.1 Static timing analysis 207
7.4.2 DTA vs.STA 210
7.4.3 Circuit simulation in STA 210
7.5 Interconnect Model and Circuit Order Reduction 211
7.5.1 Lumped RC vs.distributed RLC model 211
7.5.2 Circuit order reduction 212
7.6 Low Power Design 216
7.7 Design for Manufacture 219
7.8 High-level Synthesis 225
7.9 Performance Bound Evaluation 226
7.10 Summary 229
7.11 Problems 229
References 230
Chapter 8 Verification and Testing 233
8.1 Introduction 234
8.2 Digital Circuits Test 236
8.2.1 Fault modeling 237
8.2.2 Fault simulation 240
8.2.3 Test generation for combinational logic 242
8.2.4 Test generation for sequential logic 245
8.2.5 ATPG using TetraMAX 250
8.3 BIST 252
8.3.1 The concept of BIST 252
8.3.2 TPG 253
8.3.3 ORA 260
8.3.4 BIST architectures 266
8.4 Scan and Boundary Scan 271
8.4.1 Digital DFT for scan 271
8.4.2 Scan chains 276
8.4.3 Digital boundary scan standard-IEEE 1149.1 281
8.5 Summary 286
8.6 Problems 286
References 289
Appendix A A MSDAP 290
A.1 Introduction 291
A.2 A MSDAP 291
Appendix B A C-Program Implementing the Algorithm of the MSDAP 298
B.1 Introduction 299
B.2 The MSDAP Computation Method in C-Code 299
Appendix C An FSM for the MSDAP Operation Mode 313
C.1 Introduction 314
C.2 An FSM for the Operation Mode and System Setting 314
Appendix D A Sample Project MSDAP Report 326
D.1 Introduction 327
D.2 A Sample Project MSDAP Report 327