数字设计与Verilog实现 第5版 英文版

1 Digital Systemsand Binary Numbers 17

1.1 Digital Systems 17

1.2 Binary Numbers 19

1.3 Number-Base Conversions 22

1.4 Octal and Hexadecimal Numbers 24

1.5 Complements of Numbers 26

1.6 Signed Binary Numbers 30

1.7 Binary Codes 34

1.8 Binary Storage and Registers 43

1.9 Binary Logic 46

2 Boolean Algebra and Logic Gates 54

2.1 Introduction 54

2.2 Basic Definitions 54

2.3 Axiomatic Definition of Boolean Algebra 56

2.4 Basic Theorems and Properties of Boolean Algebra 59

2.5 Boolean Functions 62

2.6 Canonical and Standard Forms 67

2.7 Other Logic Operations 74

2.8 Digital Logic Gates 76

2.9 Integrated Circuits 82

3 Gate-Level Minimization 89

3.1 Introduction 89

3.2 The Map Method 89

3.3 Four-Variable K-Map 96

3.4 Product-of-Sums Simplification 100

3.5 Don't-Care Conditions 104

3.6 NAND and NOR Implementation 106

3.7 Other Two-Level Implementations 113

3.8 Exclusive-OR Function 119

3.9 Hardware Description Language 124

4 Combinational Logic 141

4.1 Introduction 141

4.2 Combinational Circuits 141

4.3 Analysis Procedure 142

4.4 Design Procedure 145

4.5 Binary Adder-Subtractor 149

4.6 Decimal Adder 160

4.7 Binary Multiplier 162

4.8 Magnitude Comparator 164

4.9 Decoders 166

4.10 Encoders 171

4.11 Multiplexers 174

4.12 HDL Models of Combinational Circuits 180

5 Synchronou s Sequential Logic 206

5.1 Introduction 206

5.2 Sequential Circuits 206

5.3 Storage Elements:Latches 209

5.4 Storage Elements:Flip-Flops 212

5.5 Analysis of Clocked Sequential Circuits 220

5.6 Synthesizable HDL Models of Sequential Circuits 233

5.7 State Reduction and Assignment 247

5.8 Design Procedure 252

6 Registers and Counters 271

6.1 Registers 271

6.2 Shift Registers 274

6.3 Ripple Counters 282

6.4 Synchronous Counters 287

6.5 Other Counters 294

6.6 HDL for Registers and Counters 299

7 Memory and Programmable Logic 315

7.1 Introduction 315

7.2 Random-Access Memory 316

7.3 Memory Decoding 323

7.4 Error Detection and Correction 328

7.5 Read-Only Memory 331

7.6 Programmable Logic Array 337

7.7 Programmable Array Logic 341

7.8 Sequential Programmable Devices 345

8 Design at the Register Transfer Level 367

8.1 Introduction 367

8.2 Register Transfer Level Notation 367

8.3 Register Transfer Levelin HDL 370

8.4 Algorithmic State Machines（ASMs） 379

8.5 Design Example （ASMD Chart） 387

8.6 HDL Description of Design Example 397

8.7 Sequential Binary Multiplier 407

8.8 Control Logic 412

8.9 HDL Description of Binary Multiplier 418

8.10 Design with Multiplexers 427

8.11 Race-Free Design（Software Race Conditions） 438

8.12 Latch-Free Design（Why Waste Silicon？） 441

8.13 Other Language Features 442

9 Laboratory Experiments with Standard ICs and FPGAs 454

9.1 Introduction to Experiments 454

9.2 Experiment 1:Binary and Decimal Numbers 459

9.3 Experiment 2:Digital Logic Gates 462

9.4 Experiment 3:Simplification of Boolean Functions 464

9.5 Experiment 4:Combinational Circuits 466

9.6 Experiment 5:Code Converters 468

9.7 Experiment 6:Design with Multiplexers 469

9.8 Experiment 7:Adders and Subtractors 471

9.9 Experiment 8:Flip-Flops 473

9.10 Experiment 9:Sequential Circuits 476

9.11 Experiment 10:Counters 477

9.12 Experiment 11:Shift Registers 479

9.13 Experiment 12:Serial Addition 482

9.14 Experiment 13:Memory Unit 483

9.15 Experiment 14:Lamp Handball 485

9.16 Experiment 15:Clock-Pulse Generator 489

9.17 Experiment 16:Parallel Adder and Accumulator 491

9.18 Experiment 17:Binary Multiplier 494

9.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs 496

10 Standard Graphic Symbols 504

10.1 Rectangular-Shape Symbols 504

10.2 Qualifying Symbols 507

10.3 Dependency Notation 509

10.4 Symbols for Combinational Elements 511

10.5 Symbols for Flip-Flops 513

10.6 Symbols for Registers 515

10.7 Symbols for Counters 518

10.8 Symbol for RAM 520

Appendix 523

Answers to Selected Problems 537

Index 555