- 作 者：（美）Nicholas Carter著
- 出 版 社：北京：机械工业出版社
- 出版年份：2002
- ISBN：7111104188
- 标注页数：306 页
- PDF页数：315 页
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CHAPTER 1 Introduction 1
1.1 Purpose of This Book 1
1.2 Background Assumed 1
1.3 Material Covered 1
1.4 Chapter Objectives 2
1.5 Technological Trends 2
1.6 Measuring Performance 3
1.7 Speedup 6
1.8 Amdahl's Law 6
1.9 Summary 7
Solved Problems 8
CHAPTER 2 Data Representations and Computer Arithmetic 16
2.1 Objectives 16
2.2 From Electrons to Bits 16
2.3 Binary Representation of Positive Integers 18
2.4 Arithmetic Operations on Positive Integers 19
2.5 Negative Integers 23
2.6 Floating-Point Numbers 28
2.7 Summary 35
Solved Problems 36
CHAPTER 3 Computer Organization 45
3.1 Objectives 45
3.2 Introduction 45
3.3 Programs 46
3.4 Operating Systems 50
3.5 Computer Organization 53
3.6 Summary 57
Solved Problems 57
4.1 Objectives 63
4.2 Introduction 63
CHAPTER 4 Programming Models 63
4.3 Types of Instructions 65
4.4 Stack-Based Architectures 70
4.5 General-Purpose Register Architectures 78
4.6 Comparing Stack-Based and General-Purpose Register Architectures 83
4.7 Using Stacks to Implement Procedure Calls 84
4.8 Summary 86
Solved Problems 87
CHAPTER 5 Processor Design 94
5.1 Objectives 94
5.2 Introduction 94
5.3 Instruction Set Architecture 95
5.4 Processor Microarchitecture 103
5.5 Summary 107
Solved Problems 108
6.2 Introduction 115
CHAPTER 6 Pipelining 115
6.1 Objectives 115
6.3 Pipelining 116
6.4 Instruction Hazards and Their Impact on Throughput 120
6.5 Predicting Execution Time in Pipelined Processors 126
6.6 Result Forwarding(Bypassing) 130
6.7 Summary 133
Solved Problems 134
CHAPTER 7 Instruction-Level Parallelism 144
7.1 Objectives 144
7.2 Introduction 144
7.3 What is Instruction-Level Parallelism? 146
7.4 Limitations of Instruction-Level Parallelism 147
7.5 Superscalar Processors 149
7.6 In-Order versus Out-of-Order Execution 149
7.7 Register Renaming 153
7.8 VLIW Processors 156
7.9 Compilation Techniques for Instruction-Level Parallelism 159
7.10 Summary 162
Solved Problems 164
CHAPTER 8 Memory Systems 175
8.1 Objectives 175
8.2 Introduction 175
8.3 Latency,Throughput,and Bandwidth 176
8.4 Memory Hierarchies 179
8.5 Memory Technologies 183
8.6 Summary 190
Solved Problems 191
CHAPTER 9 Caches 198
9.1 Objectives 198
9.2 Introduction 198
9.3 Data Caches,Instruction Caches,and Unified Caches 199
9.4 Describing Caches 200
9.5 Capacity 201
9.6 Line Length 201
9.7 Associativity 203
9.8 Replacement Policy 208
9.9 Write-Back versus Write-Through Caches 210
9.10 Cache Implementations 212
9.11 Tag Arrays 212
9.12 Hit/Miss Logic 214
9.13 Data Arrays 214
9.14 Categorizing Cache Misses 216
9.15 Multilevel Caches 217
9.16 Summary 219
Solved Problems 219
10.2 Introduction 229
10.1 Objectives 229
CHAPTER 10 Virtual Memory 229
10.3 Address Translation 230
10.4 Demand Paging versus Swapping 233
10.5 Page Tables 234
10.6 Translation Lookaside Buffers 239
10.7 Protection 243
10.8 Caches and Virtual Memory 245
10.9 Summary 247
Solved Problems 248
CHAPTER 11 I/O 255
11.1 Objectives 255
11.2 Introduction 255
11.3 I/O Buses 256
11.4 Interrupts 258
11.5 Memory-Mapped I/O 262
11.6 Direct Memory Access 264
11.7 I/O Devices 265
11.8 Disk Systems 266
11.9 Summary 270
Solved Problems 271
CHAPTER 12 Multiprocessors 279
12.1 Objectives 279
12.2 Introduction 279
12.3 Speedup and Performance 280
12.4 Multiprocessor Systems 282
12.5 Message-Passing Systems 285
12.6 Shared-Memory Systems 286
12.7 Comparing Message-Passing and Shared Memory 293
12.8 Summary 294
Solved Problems 295
INDEX 303